Can we declare Schmitt triggers to have memory? Can we call their output levels states?

My answer to SE EE question Can we declare Schmitt triggers to have memory? Can we call their output levels states?

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An interesting question asked a week ago that made me think again about this phenomenon... I was able to write my answer before it was closed with the reason "opinion-based"...

Answer

The hysteresis phenomenon caught my attention in the early 80's when I invented a magnetically controlled electric switch and later applied it as an ARM/DISARM device in alarm systems. I have been thinking for a long time about the philosophy behind the legendary circuits of Schmitt trigger, RS latch and SRAM memory cell... and what they have in common. Ten years ago, I revealed the fundamental idea of making a hysteresis on the Wikipedia page about the Schmitt trigger. This question, the comments and answers below it, made me think deeply about all this again... and today the picture became clearer. This made me feel as excited as any other time when I realize a great circuit idea... and I am in a hurry to share it with you...

A) All these building blocks are the same circuits with reinforcing positive feedback that forces them to stand alone in one of their two extreme states; so all they possess memory. The difference between them is only in the way we force (toggle) them to change their current state with the opposite:

1. In a Schmitt trigger, we do it in an arithmetic way by summing the input voltage with the feedback voltage.
2. In an RS latch, we do it in a logical way by forcing the output of the logic gate to be in a certain state. We do this "politely" by means of a second input of the logic element (during this time the first input is "disconnected" from the output).
3. In an SRAM memory cell, we do it "brutally" by applying the input voltage directly to the output of the logic gate (connecting the memory cell outputs to the data lines by turning on the pass transistors).

B) To see the memory property, in all these cases, we have to return the input signal to its inactive (neutral) state:

1. In a Schmitt trigger, we have to set the input voltage inside the hysteresis loop (usually, in the middle between the high and low voltage threshold).
2. In an RS latch, we have to set the input voltage high (NAND gates) or low (NOR gates).
3. In an SRAM memory cell, we have to disconnect the memory cell outputs from the data lines by turning off the pass transistors.
4. If we do not return the input signal to its inactive (neutral) state, all these circuits will be forced to remain in the last state. This only makes sense for the Schmitt trigger.

C) Here the question arises, “Why are there different ways to manage the same devices?"

1. The Schmitt trigger is implemented by a single device (non-inverting amplifier). Therefore, we can change its state by affecting one place (feedback) in two different ways (above the upper threshold and below the lower threshold). We do this with the help of a summing device (usually, two resistors).
2. The RS latch and SRAM memory cell are implemented by two cascaded devices (a non-inverting amplifier consisting of two cascaded inverting amplifiers). To change their state, we have to affect alternately two places in the same way. Once affected one place (S), it no longer works ... we have to affect another (R).

D) Interesting questions would be, "Can we make an RS latch by a Schmitt trigger?" and "Can we make a Schmitt trigger by an RS latch?" Why not? I think we can...

My comments

1. "Something in between" in circuits with hysteresis, like "high-impedance state" in 3-state buffers, is not another (third) logic state; it is an electric state. Schmitt trigger is just an RS latch whose one input (R) is inverted and joined with the other input (S) like a D flip-flop with a level clock. In the 555 timer, the two inputs can be separated. There are such applications where 555 is used as an RS latch. 
2. The clever trick of this connection is that the two inputs have thresholds... and "the input condition where the latch retains its previous state" is between the thresholds. I think this is not a third logic state and this is not a 3-state logic. I realized this trick just before I wrote this comment and hurried to share it. There is no such possibility in a D flip-flop with a level clock. There the clock does it...