Posts

Showing posts from June, 2023

Output voltage level of TTL gate

Image
I  answered  this  SE EE question  on June 3, 2023. This is my latest (to date) CircuitLab story dedicated to the famous TTL logic gate family. How do we demystify TTL output stage? TTL circuits are some of the strangest creations of circuit designers (perhaps rivaled only by ECL circuits). If we type in the Google window "transistor-transistor logic", more than 18 million pages will pop up telling us "this is so..." but we will hardly find any pages that say "why this is exactly so..." We have no choice but to try to answer our own questions. There are two oddities in these creations - first in their input part and then in their output part. Here, the object of our attention is their output part. Reinventing TTL output stage I am not a circuit designer, just a "circuit thinker"... and I can only guess what the designers had in mind in the 60's. What I can do is try to reproduce their train of thought in the form of an imaginary pseudo-invent