Why does the TTL NAND gate use a 4 transistor design instead of 2?
This is my answer to SE EE question Why does the TTL NAND gate use a 4 transistor design instead of 2 ? My answer Since the output part has been considered so far, I will make some assumptions about the input part that implements the logic function AND (NAND). Basic logic idea As a rule, basic logic functions OR and AND are implemented by connecting *electrically-controlled switches* in parallel and series. These techniques are widely used in MOS and CMOS logic gates... and also, in the second OP's circuit where transistors are used as switches. But how is this implemented in the first OP's circuit? Here, diode elements (T1's base-emitter junctions) are used as switches that, according to the rule, should be connected in series . But diode switches cannot be connected this way because they cannot be controlled. The problem of diodes is that they are 2-terminal (1-port) switches where the input and output occupy the same two terminals anode and cathode (base and e...